In order to transmit and receive circuit and packet-switched voice and data traffic in a multi-user wireless communications environment, with services such as voice, video, image, data, fax, IP-based traffic transmissions, etc., it is necessary to employ a base-station transceiver system (hereafter referred to as “BTS”). A BTS provides a link for sending and receiving wireless communications within a localized region. Recently, there has been an increase in demand for different types of wireless communication services.
This has led to the need for data services (the term “data services” includes both voice and data services) requiring greater bandwidths and an increased number of channels. In addition, there is a growing need for BTSs to support multiple standards and protocols (i.e., service classes). Traditional signal processing architectures, such as that shown in FIG. 1, do not accommodate enough channels of each service class to satisfy the needs of these data services.
The prior art signal processing architecture shown in FIG. 1 shows a processor 108 that performs signal processing to condition, mix, and filter a signal residing on a radio frequency (RF) carrier. The RF signal is initially received at an antenna 90, is processed by radio frequency circuitry 92 and intermediate frequency (IF) circuitry 94, prior to being digitized with an analog-to-digital (A/D) converter 96. The processor 108 delivers a signal to a system 109, which includes individual circuits 110A–N for each time slot or code slot. A per-time-slot system is used in TDMA based multiple access communication systems. A per-code-slot system is used in CDMA based multiple access communication systems.
Each circuit 110 is typically realized as a single-bus shared memory co-processing architecture which includes at least one application specific fixed function integrated circuit 114, one digital signal processor 116, and one memory 118 for processing data in that channel. A problem associated with the traditional signal processing architecture, such as that shown in FIG. 1, is an inadequate level of integration when the number of channels and the data rate increase. This is due to the single bus, shared-memory architecture. Typically, as the number of channels increases, an increase in the system operating frequency is required. This is typically manifested by using a traditional digital signal processor at a very high clock speed to support this higher channel density. An increasingly greater portion of this increased horsepower is used up in being able to read and write data into memory fast enough. This results in practical implementations of these single-bus shared-memory architectures requiring a greater than linear increase in clock speed to obtain a linear increase in the channel density. In the prior art, the level of integration, such as trunking efficiency, is typically increased by increasing the speed and/or number of digital signal processors on a circuit 110. The problem with this approach is that achieving increased channel demodulation and decoding processing power is often at the expense of significantly increased power dissipation, silicon area and product cost.
The problems of inadequate efficiency, demand for greater bandwidths, and more channels per data service have necessitated the development of an efficient, cost effective mechanism for the processing of wireless data.